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October 2000
(R)
AS6UA25616
2.3V to 3.6V 256Kx16 IntelliwattTM low-power CMOS SRAM with one chip enable `Features
* * * * * * * AS6UA25616 IntelliwattTM active power circuitry Industrial and commercial temperature ranges available Organization: 262,144 words x 16 bits 2.7V to 3.6V at 55 ns 2.3V to 2.7V at 70 ns Low power consumption: ACTIVE - 114 mW at 3.6V and 55 ns - 68 mW at 2.7V and 70 ns * Low power consumption: STANDBY - 72 W max at 3.6V - 41 W max at 2.7V * 1.2V data retention * Equal access and cycle times * Easy memory expansion with CS, OE inputs * Smallest footprint packages - 48-ball FBGA - 400-mil 44-pin TSOP II * ESD protection 2000 volts * Latch-up current 200 mA
Logic block diagram
A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1-I/O8 I/O9-I/O16 WE Row Decoder VCC 256K x 16 Array (4,194,304) VSS
Pin arrangement (top view)
44-pin 400-mil TSOP II 44 A4 1 A5 A6 43 A3 2 A2 A7 42 3 OE 41 A1 4 A0 5 UB 40 CS 6 39 LB I/O16 7 38 I/O1 I/O15 8 37 I/O2 I/O14 9 36 I/O3 I/O13 10 35 I/O4 VCC VSS 11 34 VSS VCC 12 33 13 32 I/O5 I/O12 14 31 I/O6 I/O11 15 30 I/O7 I/O10 I/O8 16 29 I/O9 17 28 WE NC 18 A17 27 A8 19 26 A9 A16 20 25 A15 A10 24 A11 A14 21 23 A12 A13 22
I/O buffer
Control circuit Column decoder A5 A9 A10 A11 A14 A15 A16 A17
UB OE LB CS
48-CSP Ball-Grid-Array Package
A B C D E F G H
1 LB I/O9 I/O10 VSS VCC I/O15 I/O16 NC
2 OE UB I/O11 I/O12 I/O13 I/O14 NC A8
3 A0 A3 A5 A17 NC A14 A12 A9
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CS I/O2 I/O4 I/O5 I/O6 WE A11
6 NC I/O1 I/O3 VCC V SS I/O7 I/O8 NC
Selection guide
VCC Range Product AS6UA25616 AS6UA25616 Min (V) 2.7 2.3 Typ2 (V) 3.0 2.5 Max (V) 3.6 2.7 Speed (ns) 55 70 Power Dissipation Operating (ICC) Max (mA) 2 1 Standby (ISB1) Max (A) 20 15
10/6/00
ALLIANCE SEMICONDUCTOR
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Copyright (c)2000 Alliance Semiconductor. All rights reserved.
AS6UA25616
(R)
Functional description
The AS6UA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words x 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 55/70 ns are ideal for low-power applications. Active high and low chip enables (CS) permit easy memory expansion with multiple-bank memory systems. When CS is high, or UB and LB are high, the device enters standby mode: the AS6UA25616 is guaranteed not to exceed 72 W power consumption at 3.6V and 55 ns; 41W at 2.7V and 70 ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption. A write cycle is accomplished by asserting write enable (WE) and chip enable (CS) low, and UB and/or LB low. Data on the input pins I/O1-O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), chip enable (CS), UB and LB low, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or wri e enable is t active, or (UB) and (LB), output drivers stay in high-impedance mode. These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to bewritten and read. LB controls the lower bits, I/O1-I/O8, and UB controls the higher bits, I/O9-I/O16. All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.3V to 3.6V supply. Device is available in the JEDEC standard 400-mm, TSOP II, and 48-ball FBGA packages.
Absolute maximum ratings
Parameter Voltage on VCC relative to V SS Voltage on any I/O pin relative to GND Power dissipation Storage temperature (plastic) Temperature with VCC applied DC output current (low) Device Symbol VtIN VtI/O PD Tstg Tbias IOUT Min -0.5 -0.5 - -65 -55 - 1.0 +150 +125 20 Max VCC + 0.5 Unit V V W
o
C
oC
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CS H L L L WE X X H H OE X X H L LB X H X L H L L L L X H L
Key: X = Don't care, L = Low, H = High.
UB X H X H L L H L L
Supply Current ISB ICC ICC
I/O1-I/O8 High Z High Z DOUT High Z DOUT DIN
I/O9-I/O16 High Z High Z High Z DOUT DOUT High Z DIN DIN
Mode Standby (ISB) Output disable (ICC) Read (ICC)
ICC
High Z DIN
Write (I CC)
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ALLIANCE SEMICONDUCTOR
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AS6UA25616
(R)
Recommended operating condition (over the operating range)
Parameter VOH Description IOH = -2.1mA Output HIGH Voltage IOH = -0.5mA VOL Output LOW Voltage IOL = 2.1mA IOL = 0.5mA VIH Input HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 2.3V VCC = 2.7V VCC = 2.3V VCC = 2.7V V IL IIX IOZ ICC Input LOW Voltage VCC = 2.3V Input Load Current Output Load Current VCC Operating Supply Current GND < VIN < VCC GND < VO < VCC; Outputs High Z CS = VIL, VIN = V IL or VIH, IOUT = 0mA, f=0 VCC = 3.6V VCC = 2.7V VCC = 3.6V VCC = 2.7V VCC = 3.6V (55/70 ns) VCC = 2.7V (70 ns) VCC = 3.6V VCC = 2.7V VCC = 3.6V VCC = 2.7V VCC = 1.2V -0.3 -1 -1 0.6 +1 +1 2 mA 1 5 mA 4 40/30 mA 25 100
A A A
Test Conditions VCC = 2.7V
Min 2.4
Max
Unit V
2.0 0.4 V 0.4 2.2 2.0 -0.5 VCC + 0.5 VCC + 0.3 0.8 V V
ICC1 @ 1 MHz
CS < 0.2V, VIN < 0.2V Average VCC Operating or VIN > VCC - 0.2V, Supply Current at 1 MHz f = 1 mS Average VCC Operating CS VIL, VIN = VIL or Supply Current VIH, f = fMax CS > VIH or UB = LB CS Power Down Current; > VIH, other inputs = TTL Inputs VIL or V IH, f = 0 CS Power Down Current; CMOS Inputs
CS > VCC - 0.2V or UB = LB > VCC - 0.2V, other inputs = 0V - VCC, f = f Max
ICC2
ISB
100 20 15 2
A A
ISB1
ISBDR
Data Retention
CS > VCC - 0.1V, UB = LB = VCC - 0.1V f=0
Capacitance (f = 1 MHz, Ta = Room temperature, VCC = NOMINAL)2
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CS, WE, OE, LB, UB I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF
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ALLIANCE SEMICONDUCTOR
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AS6UA25616
(R)
Read cycle (over the operating range)3,9
-55 Parameter Read cycle time Address access time Chip enable (CS) access time Output enable (OE) access time Output hold from address change CS low to output in low Z Symbol tRC tAA tACS tOE tOH tCLZ Min 55 - - - 10 10 0 5 - 10 0 0 0 - Max - 55 55 25 - - 20 - 55 - 20 20 - 55 Min 70 - - - 10 10 0 5 - 10 0 0 0 - -70 Max - 70 70 35 - - 20 - 70 - 20 20 - 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 4, 5 4, 5 5 4, 5 4, 5 4, 5 3 3 Notes
CS high to output in high Z tCHZ OE low to output in low Z tOLZ UB/LB access time UB/LB low to low Z UB/LB high to high Z tBA tBLZ tBHZ
OE high to output in high Z tOHZ Power up time tPU Power down time tPD
Key to switching waveforms
Rising input Falling input tRC Address tOH DOUT Previous data valid tAA Data valid tOH Undefined/don't care
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (CS, OE, UB, LB controlled)3,6,8,9
tRC Address tAA OE tOLZ CS tACS tLZ LB, UB tBLZ DOUT tBA Data valid tBHZ tOHZ tHZ tOE tOH
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ALLIANCE SEMICONDUCTOR
10/6/00
AS6UA25616
(R)
Write cycle (over the operating range)11
-55 Parameter
Write cycle time Chip enable to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end UB/LB low to end of write
-70 Max - - - - - - - - 20 - - Min 70 60 60 0 55 0 30 0 0 5 55 Max - - - - - - - - 20 - - Unit ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 12 12 Notes
Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW tBW
Min 55 40 40 0 35 0 25 0 0 5 35
Write waveform 1 (WE controlled)10,11
tWC Address tCW CS tBW LB, UB tAS WE tDW DIN DOUT Data undefined tWZ Data valid tOW High Z tDH tAW tWP tAH
Write waveform 2 (CS controlled)10,11
tWC Address tAS CS tCW tAW tBW LB, UB tWP WE tDW DIN DOUT tCLZ High Z tWZ Data undefined Data valid tOW High Z tDH tAH
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ALLIANCE SEMICONDUCTOR
5
AS6UA25616
(R)
Data retention characteristics (over the operating range) 13,5
Parameter VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Symbol VDR ICCDR tCDR tR Test conditions VCC = 1.2V CS VCC - 0.1V or UB = LB = > VCC - 0.1V V IN VCC - 0.1V or VIN 0.1V Min 1.2V - 0 tRC Max 3.6 4 - - Unit V A ns ns
Data retention waveform
Data retention mode VCC VCC tCDR CS VIH VDR VIH VDR 1.2V VCC tR
AC test loads and waveforms
VCC OUTPUT 30 pF R2 INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE R1 VCC OUTPUT 5 pF R2 VCC Typ GND (b) Thevenin equivalent: R1 OUTPUT ALL INPUT PULSES 90% 10% < 5 ns (c) 90% 10% RTH V
(a)
Parameters R1 R2 RTH VTH
VCC = 3.0V 1105 1550 645 1.75V
VCC = 2.5V 16670 15380 8000 1.2V
VCC = 2.0V 15294 11300 6500 0.85V
Unit Ohms Ohms Ohms Volts
Notes 1 During VCC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification. 2 This parameter is sampled, but not 100% tested. 3 For test conditions, see AC Test Conditions. 4 tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500 mV from steady-state voltage. 5 This parameter is guaranteed, but not tested. 6 WE is HIGH for read cycle. 7 CS and OE are LOW for read cycle. 8 Address valid prior to or coincident with CS transition LOW. 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle. 11 All write cycle timings are referenced from the last valid address to the first transitioning address. 12 N/A. 13 1.2V data retention applies to commercial and industrial temperature range operations. 14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
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ALLIANCE SEMICONDUCTOR
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AS6UA25616
(R)
Typical DC and AC characteristics
Normalized supply current vs. supply voltage 1.4 1.2 Normalized ICC 1.0 0.8 0.6 0.4 0.2 0.0 1.7 2.2 2.7 3.2 3.7 VIN = VCC typ TA = 25 C 1.0 Normalized access time vs. supply voltage 3.0 2.5 Normalized TAA Normalized ISB2 0.75 TA = 25 C 0.5 2.0 1.5 1.0 0.5 0.0 -0.5 0.0 1.7 2.2 2.7 3.2 3.7 -55 25 105 Ambient temperature (C) Normalized ICC vs. Cycle Time 1.5 VCC = 3.6V TA = 25 C VCC = VCC typ VIN = VCC typ Normalized standby current vs. ambient temperature
0.25
Supply voltage (V) Normalized standby current vs. supply voltage 1.4 1.2 Normalized ISB 1.0 0.8 0.6 0.4 0.2 0.0 1 2.8 1.9 Supply voltage (V) 3.7 VIN = VCC typ TA = 25 C ISB2
Supply Voltage (V)
Normalized ICC
1.0
0.50
0.10 1 5 10 Supply voltage (V) 15
Package diagrams and dimensions
44-pin TSOP II
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
c
Min (mm) A
44-pin TSOP II e He
Max (mm) 1.2
A1 A2 b
0.05 0.95 0.25 20.85 10.06 11.56 0.40 1.05 0.45 21.05 10.26 11.96 0.60
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
d
c d e He E l
0.15 (typical)
A A1 b E
A2 0-5
l
0.80 (typical)
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ALLIANCE SEMICONDUCTOR
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AS6UA25616
(R)
48-ball FBGA Bottom View 6 5 4 3 2 1 Ball #A1 Top View Ball #A1 Index
A B C D E F G H Elastomer A B1 B A C1 SRAM Die C
Side View
Detail View A
E2 E
D E2 E Die E1 Die 0.3/Typ Y
Minimum A B B1 C C1 D E E1 E2 Y - 6.90 - 10.90 - 0.30 - - 0.22 -
Typical 0.75 7.00 3.75 11.00 5.25 0.35 - 0.68 0.25 -
Maximum - 7.10 - 11.10 - 0.40 1.20 - 0.27 0.08
Notes 1. Bump counts: 48 (8 row x 6 column). 2. Pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3. Units: millimeters. 4. All tolerance are 0.050 unless otherwise specified. 5. Typ: typical. 6. Y is coplanarity: 0.08 (max).
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ALLIANCE SEMICONDUCTOR
10/6/00
AS6UA25616
(R)
Ordering codes
Speed (ns) 55/70
Ordering Code
AS6UA25616-TC AS6UA25616-BC AS6UA25616-TI AS6UA25616-BI
Package Type
44-pin TSOP II 48-ball fine pitch BGA 44-pin TSOP II 48-ball fine pitch BGA
Operating Range Commercial
55/70
Industrial
Part numbering system
AS6UA SRAM IntelliwattTM prefix 25616 Device number T, B Package: T: TSOP II B: CSP BGA C, I Temperature range: C: Commercial: 0 C to 70 C IL Industrial: -40 C to 85 C
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ALLIANCE SEMICONDUCTOR
10/6/00
Copyright (c)2000 Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and IntelliwattTM are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this web site and its products at any time without no tice. Alliance assumes no responsibility for any errors that may appear in this web site. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as expressly agreed to in Alliance's Terms and Conditions of Sale (available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indem nify Alliance against all claims arising from such use.

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